REUSE 2017

Dec 14, 2017
2:00 PM PT

Speaker: Dr. Tim Saxe
Location: Santa Clara Convention Center

Additional Information

Slash the cost and time of SoC design reuse

For years now system designers have leveraged standalone FPGAs to augment existing designs in order to get to market first.  In the early days, FPGAs with useful gate counts required a whole die to implement.  Today, FPGAs with useful gate counts can fit in a few square millimeters, which makes it practical to integrate SoCs and FPGAs in one device.  And that means you can build SoC platforms where the standard part is implemented in fixed logic and the differentiated part is implemented as an embedded FPGA.  This approach allows SoC design to be leveraged into different market segments and new market segments by programming the FPGA portion – which doesn’t require a new layout, new physical design verification or new masks.

Booth #8

QuickLogic will demonstrate how its newest ArcticPro eFPGA technology is enabling developers to create SoC and ASIC platforms that can easily be tailored to serve multiple target applications. 


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REUSE 2017

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